Generally, the double diffused drain (DDD) structure has been used to improve the hot carrier effect and the like of a semiconductor device having a channel length greater than 0.35 μm. Such a device is not concerned about breakdown voltage (BVDss) between source and drain as well as roll-off of threshold voltage.
More recently, as channel length is shortened to achieve a high degree of integration in semiconductor devices to raise the short channel effect, the DDD structure is being used less. However, it is advantageous for a low power device to have high threshold voltage and BVDss in securing junction leakage. As a result, the DDD structure is employed in part. Yet, the short channel device still has the above-noted difficulty in employing the DDD structure. For instance, a transistor as a low power device having small leakage current tends to employ the LDD (lightly doped drain) structure instead of the conventional DDD structure to enhance the short channel effect due to the reduced channel length. As the junction configuration is modified, the breakdown voltage between source and drain is lowered. This may be explained as follows. When the LDD dopant increases, a junction between N-type LDD and a P-type well is abruptly formed to increase leakage from the junction region. Meanwhile, the known process of implanting additional P-type dopant is mainly used in improving leakage characteristic and capacitance by grading a junction profile, not in the LDD region but in the source/drain region.
FIG. 1A is a cross-sectional diagram of a known semiconductor device having a double diffused drain (DDD) and FIG. 1B is a cross-sectional diagram of a semiconductor device having a lightly doped drain (LDD). Referring to FIG. 1A, an STI layer 16 and an n-well or p-well 11 are formed on a semiconductor substrate. A gate oxide layer 12 is formed 30 Å thick on the substrate, and a polysilicon layer 13 is deposited over the substrate. A gate 13 is then formed by patterning the polysilicon layer by photolithography. Subsequently, a PMOS or NMOS DDD region 14 is formed in the N- or P-well 11 by ion implantation. A sidewall spacer 18 is provided to the gate 13 by depositing a nitride layer over the substrate and by etching back the nitride layer. Subsequently, ion implantation is carried out on the substrate using dopant of As and P ions to form source and drain regions 15 and 19, and silicidation is carried out on the substrate to form a Co-silicide 17 layer on the gate 13 and the source and drain regions 15 and 19.
Referring to FIG. 1B, a process of fabricating a semiconductor device having the LDD structure is similar to that of fabricating the semiconductor device having the DDD structure in FIG. 1A, except forming a PMOS or NMOS LDD region 24 instead of forming the PMOS or NMOS DDD region 14 in FIG. 1A by ion implantation. However, the short channel effect still takes place in case of applying the DDD or LDD structure to the known low power device. Moreover, a high electric field is applied to the LDD region.